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? integrated circuits group lh 28 f16 0 bj h e - bt l 70 fla sh me mor y 16m ( 1m 16 / 2 m x 8 ) (model no.: lh f 16 j0 7 ) spec no.: fm 99 600 3 issue date: ju ne 22 , 1 99 9 p reliminary p roduct s pecifications
sharp lhf16jo7 l handle this document carefully for it contains material protected by international copyright law. any reproduction, full or in part, of this material is prohibited without the express written permission of the company. l when using the products covered herein, please observe the conditions written herein and the precautions outlined in the following paragraphs. in no event shall the company be liable for any damages resulting from failure to strictly adhere to these conditions and precautions. (1) the products covered herein are designed and manufactured for the following application areas. when using the products covered herein for the equipment listed in paragraph (2), even for the following application areas, be sure to observe the precautions given in paragraph (2). never use the products for the equipment listed in paragraph (3). *office electronics l instrumentation and measuring equipment amachine tools l audiovisual equipment *home appliance acommunication equipment other than for trunk lines (2) those contemplating using the products covered herein for the following equipment which demands high reliability, should first contact a sales representative of the company and then accept responsibility for incorporating into the design fail-safe operation, redundancy, and other appropriate measures for ensuring reliability and safety of the equipment and the overall system. acontrol and safety devices for airplanes, trains, automobiles, and other transportation equipment l mainframe computers atraffic control systems @gas leak detectors and automatic cutoff devices orescue and security equipment l other safety devices and safety equipment, etc. (3) do not use the products covered herein for the following equipment which demands extremely high performance in terms of functionality, reliability, or accuracy. l aerospace equipment *communications equipment for trunk lines *control equipment for the nuclear power industry amedical equipment related to life support, etc. (4) please direct all queries and comments regarding the interpretation of the above three paragraphs to a sales representative of the company. l please direct all queries regarding the products covered herein to a sales representative of the company. rev. 1.2
sharp lhf16jo7 1 contents page page 1 introduction.. ............................................................ 3 1.1 features ........................................................................ 3 1.2 product overview.. ...................................................... .3 1.3 product description ...................................................... 4 1.3.1 package pinout ....................................................... 4 1.3.2 block organization ................................................. 4 2 principles of operation.. ..................................... .7 2.1 data protection.. .......................................................... .8 5 design considerations ....................................... 25 5.1 three-line output control ........................................ 25 5.2 ry/by# and wsm polling ....................................... 25 5.3 power supply decoupling ......................................... 25 5.4 v,, trace on printed circuit boards ..................... 25 5.5 v,,, v,,w, rp# transitions .................................... 25 5.6 power-up/down protection.. ..................................... 26 5.7 power dissipation ...................................................... 26 5.8 data protection method.. ........................................... 26 3 bus operation. ........................................................... 8 3.1 read.. ............................................................................ 8 3.2 output disable.. ............................................................ 8 3.3 standby.. ...................................................................... .8 3.4 reset ............................................................................. 8 3.5 read identifier codes ................................................... 9 3.6 write ............................................................................. 9 4 command definitions.. .......................................... .9 4.1 read array command ................................................ 12 4.2 read identifier codes command ............................... 12 4.3 read status register command.. ............................... 12 4.4 clear status register command ................................. 12 4.5 block erase command.. ............................................. 13 4.6 full chip erase command ......................................... 13 4.7 word/byte write command.. ..................................... 13 4.8 block erase suspend command ................................ 14 4.9 word/byte write suspend command.. ...................... 14 4.10 set block and permanent lock-bit command.. ...... .15 4.11 clear block lock-bits command ............................ 15 4.12 block locking by the wp#. ..................................... 16 6 electrical specifications ................................ 27 6.1 absolute maximum ratings ...................................... 27 6.2 operating conditions.. ............................................... 27 6.2.1 capacitance.. ........................................................ 27 6.2.2 ac input/output test conditions ........................ 28 6.2.3 dc characteristics ............................................... 29 6.2.4 ac characteristics - read-only operations.. ...... 31 6.2.5 ac characteristics - write operations ................ 34 6.2.6 alternative ce#-controlled writes.. .................... 36 6.2.7 reset operations .................................................. 38 6.2.8 block erase, full chip erase, word/byte write and lock-bit configuration performance ................. 39 rev. 1.2
shari= lhfl6507 2 LH28F160BJHE-BTL70 16m-bit ( 1mbit x16 / 2mbit x8 ) boot block flash memory n low voltage operation - v,,=vccw=2.1v-3.6v single voltage n user-configurable x8 or x 16 operation n high-performance read access time - 70n.s(v,,=2.7v-3.6v) n operating temperature - -40c to +wc n low power management - typ. 2pa (v,,=3.ov) standby current - automatic power savings mode decreases iccr in static mode - typ. 120pa (v,,=3.ov, ta=+25?c, f=32khz) read current n optimized array blocking architecture - two 4k-word (8k-byte) boot blocks - six 4k-word (8k-byte) parameter blocks - thirty-one 32k-word (64k-byte) main blocks - bottom boot location n extended cycling capability - minimum 100,000 block erase cycles n enhanced automated suspend options - word/byte write suspend to read - block erase suspend to word/byte write - block erase suspend to read n enhanced data protection features - absolute protection with v,,wiv,-, - block erase, full chip erase, word/byte write and lock-bit configuration lockout during power transitions - block locking with command and wp# - permanent locking w automated block erase, full chip erase, word/byte write and lock-bit configuration - command user interface (cui) - status register (sr) n sram-compatible write interface n industry-standard packaging - 48-lead tsop n etoxtm* nonvolatile flash technology n cmos process (p-type silicon substrate) h not designed or rated as radiation hardened sharp?s LH28F160BJHE-BTL70 flash memory is a high-density, low-cost, nonvolatile, read/write storage solution for a wide range of applications. LH28F160BJHE-BTL70 can operate at v,,=2.7v-3.6v and vccw- -2.7v-3.6v or 11.4v-12.6v. its low voltage operation capability realize battery life and suits for cellular phone application. its boot, parameter and main-blocked architecture, low voltage and extended cycling provide for highly flexible component suitable for portable terminals and personal computers. its enhanced suspend capabilities provide for an ideal solution for code + data storage applications. for secure code storage applications, such as networking, where code is either directly executed out of flash or downloaded to dram, the LH28F160BJHE-BTL70 offers four levels of protection: absolute protection with v,--wiv,,,,, selective hardware block locking or flexible software block locking. these alternatives give designers ultimate control of their code security needs. the LH28F160BJHE-BTL70 is manufactured on sharp?s 0.25pm etoxtm* process technology. it come in industry- standard package: the 48-lead tsop, ideal for board constrained applications. *etox is a trademark of intel corporation. rev. 1.2
sharp lhfl6507 3 1 introduction this datasheet contains LH28F160BJHE-BTL70 specifications. section 1 provides a flash memory overview. sections 2, 3, 4 and 5 describe the memory organization and functionality. section 6 covers electrical specifications. 1.1 features key enhancements of LH28F160BJHE-BTL70 boot block flash memory are: *single low voltage operation ~low power consumption *enhancedsuspend capabilities *boot block architecture please note following: l vccwlk has been lowered to l.ov to support 2.7v- 3.6v block erase, full chip erase, word/byte write and lock-bit configuration operations. the vccw voltage transitions to gnd is recommended for designs that switch v,,, off during read operation. 1.2 product overview the LH28F160BJHE-BTL70 is a high-performance 16m- ?it boot block flash memory organized as lm-word of 16 5ts or 2m-byte of 8 bits. the lm-word/2m-byte of data is uranged in two 4k-wor&/8k-byte boot blocks, six 4k- word/8k-byte parameter blocks and thirty-one 32k- ,vord/64k-byte main blocks which are individually erasable, lockable and unlockable in-system. the memory nap is shown in figure 3. the dedicated v ccw pin gives complete data protection when vccw$vccwlk. 4 command user interface (cud serves as the interface letween the system processor and internal operation of the levice. a valid command sequence written to the cui nitiates device automation. an internal write state tiachine (wsm) automatically executes the algorithms tnd timings necessary for block erase, full chip erase, vord/hyte write and lock-bit configuration operations. a block erase operation erases one of the device?s 32k. word/64k-byte blocks typically within 1.2s (3v v,,, 3\ vccw), 4k-word/8k-byte blocks typically within 0.6s (3\ v,,, 3v vc&) independent of other blocks. each block can be independently erased minimum 100,000 times block erase suspend mode allows system software tc suspend block erase to read or write data from any other block. writing memory data is performed in word/byte increments of the device?s 32k-word blocks typically within 33us (3v v,,, 3v v,,,), 64k-byte blocks typically within 31ps (3v v,,, 3v vccw), 4k-word blocks typically within 36ps (3v v,,, 3v v,,,), 8k- byte blocks typically within 32~s (3v v,,, 3v vccw). word/byte write suspend mode enables the system to read data or execute code from any other flash memory array location. individual block locking uses a combination of bits, thirty- nine block lock-bits, a permanent lock-bit and wp# pin, to lock and unlock blocks. block lock-bits gate block erase, full chip erase and word/byte write operations, while the permanent lock-bit gates block lock-bit modification and locked block alternation. lock-bit configuration operations (set block lock-bit, set permanent lock-bit and clear block lock-bits commands) set and cleared lock-bits. the status register indicates when the wsm?s block erase, full chip erase, word/byte write or lock-bit configuration operation is finished. the ry/by# output gives an additional indicator of wsm activity by providing both a hardware signal of status (versus software polling) and status masking (interrupt masking for background block erase, for example). status polling using ry/by# minimizes both cpu overhead and system power consumption. when low, rylby# indicates that the wsm is performing a block erase, full chip erase, word/byte write or lock-bit configuration. ry/by#-high z indicates that the wsm is ready for a new command, block erase is suspended (and word/byte write is inactive), word/byte write is suspended, or the device is in reset mode. rev. 1.2
shari= lhfl6507 4 the access time is 70ns (tav v) over the operating temperature range (-40c to + 5c) 8 and v,, supply voltage range of 2.7v-36v. the automatic power savings (aps) feature substantially reduces active current when the device is in static mode (addresses not switching). in aps mode, the typical iccr current is 2pa (cmos) at 3.ov v,,. when ce# and rp# pins are at v,,, the i,, cmos standby mode is enabled. when the rp# pin is at gnd, reset mode is enabled which minimizes power consumption and provides write protection. a reset time (tr,bqv) is required from rp# switching high until outputs are valid. likewise, the device has a wake time (tphel) from rp#-high until writes to the cui are recognized. with rp# at gnd, the wsm is reset and the status register is cleared. please do not execute reprogramming ?0? for the bit which has already been programed ?0?. overwrite operation may generate unerasable bit. in case of reprogramming ?0? to the data which has been programed ?1?. .program ?0? for the bit in which you want to change data from ?1? to ?0?. .program ?1? for the bit which has already been programmed ?0?. for example, changing data from ?10111101? to ?10111100? requires ?11111110? programming. 1.3 product description 1.3.1 package pinout LH28F160BJHE-BTL70 boot block flash memory is available in 48-lead tsop package (see figure 2). 1.3.2 block organization this product features an asymmetrically-blocked architecture providing system memory integration. each erase block can be erased independently of the others up to 100,000 times. for the address locations of the blocks, see the memory map in figure 3. boot blocks: the boot block is intended to replace a dedicated boot prom in a microprocessor or microcontroller-based system. this boot block 4k words (4,096words) features hardware controllable write- protection to protect the crucial microprocessor boot code from accidental modification. the protection of the boot block is controlled using a combination of the v,,, rp#, wp# pins and block lock-bit. parameter blocks: the boot block architecture includes parameter blocks to facilitate storage of frequently update small parameters that would normally require an eeprom. by using software techniques, the word-rewrite functionality of eeproms can be emulated. each boot block component contains six parameter blocks of 4k words (4,096 words) each. the protection of the parameter block is controlled using a combination of the vccw, rp# and block lock-bit. main blocks: the reminder is divided into main blocks for data or code storage. each 16m-bit device contains thirty- one 32k words (32,768 words) blocks. the protection of the main block is controlled using a combination of the vccw, rp# and block lock-bit. rev. 1.2
sharp lhf16507 c!i# wey oe# rp# figure 1. block diagram al5 a14 al3 al? all 40 a9 ?%j a19 nc we# rf% vccw wp# ryiby# am a17 2 2 a3 a? al 4%lead tsop standard pinout 12mm x 20mm top view a16 byte# gnd dqda-i dq7 dqm dq6 dql3 w5 dqu dq4 vcc dqii dq3 dqlo w2 dq9 dqi dqs dqo oe# gnd cl3 a0 figure 2. tsop 48-lead pinout rev. 1.2
sharp lhf16507 6 symbol tee table 1. pin descriptions name and function address inputs: inputs for addresses during read and write operations. addresses are a-1 a,-?% 9 internally latched during a write cycle. input a-,: lower address input while bytes is v,. a-, pin changes dq,, pin while byte# is vi,. a,5-a,g: main block address. a12-a,g: boot and parameter block address. data input/outputs: inputs data and commands during cui write cycles; outputs data input/ during memory array, status register and identifier code read cycles. data pins float to high- 'qo-dqi, ou?ljjut impedance when the chip is deselected or outputs are disabled. data is internally latched during a write cycle. dqs-dq,, pins are not used while byte mode (byte#=v,). then, dqls pin changes a-, address input. ce# rp# oe# we# input chip enable: activates the device?s control logic, input buffers, decoders and sense amplifiers. ce#-high deselects the device and reduces power consumption to standby levels. reset: resets the device internal automation. rp#-high enables normal operation. when driven input low, rp# inhibits write operations which provides data protection during power transitions. exit from reset mode sets the device to read array mode. rp# must be v,, during power-up. input output enable: gates the device?s outputs during a read cycle. input write enable: controls writes to the cui and array blocks. addresses and data are latched on the rising edge of the we# pulse. wp# write protect: when wp# is v,,, boot blocks cannot be written or erased. when wp# is input v,, locked boot blocls can not be written or erased. wp# is not affected parameter and main blocks. byte# byte enable: byte# v, places device in byte mode (x8). all data is then input or output on input dq,,, and dq8-r5 float. byte# v,, places the device in word mode (x16), and turns off the a-, input buffer. open ready/busy#: indicates the status of the internal wsm. when low, the wsm is performing an rylby# &!i!#& internal operation (block erase, full chip erase, word/byte write or lock-bit configuration). ry/by#-high z indicates that the wsm is ready for new commands, block erase is suspended, and word/byte write is inactive, word/byte write is suspended, or the device is in reset mode. block erase, full chip erase, word/byte write or lock-bit configuration power supply: for erasing array blocks, writing words/bytes or configuring lock-bits. with v,cwlv,,,,, memory contents cannot be altered. block erase, full vccw supply chip erase, word/byte write and lock-bit configuration with an invalid v,, (see 6.2.3 dc characteristics) produce spurious results and should not be attempted. applying 12vti.6v to v,,, during erase/write can only be done for a maximum of 1000 cycles on each block. vccw may be connected to 12vko.6v for a total of 80 hours maximum. device power supply: do not float any power pins. with vc,+v,,o, all write attempts to ?cc supply the flash memory are inhibited. device operations at invalid v,, voltage (see 6.2.3 dc characteristics) produce spurious results and should not be attempted. gnd supply ground: do not float any ground pins. nc no connect: lead is not internal connected; it may be driven or floated. rev. 1.2
shari= lhf16507 7 2 principles of operation the lh28f160bji-ebtl70 flash memory includes an on-chip wsm to manage block erase, full chip erase, word/byte write and lock-bit configuration functions. it allows for: 100% l-il-level control inputs, fixed power supplies during block erase, full chip erase, word/byte write and lock-bit configuration, and minimal processor overhead with ram-like interface timings. after initial device power-up or return from reset mode (see section 3 bus operations), the device defaults to read array mode. manipulation of external memory control pins allow array read, standby and output disable operations. status register and identifier codes can be accessed through the cui independent of the v,,, voltage. high voltage on vccw enables successful block erase, full chip erase, word/byte write and lock-bit configurations. all functions associated with altering memory contents-block erase, full chip erase, word/byte write, lock-bit configuration, status and identifier codes-are accessed via the cui and verified through the status register. commands are written using standard microprocessor write timings. the cui contents serve as input to the wsm, which controls the block erase, full chip erase, word/byte write and lock-bit configuration. the internal algorithms are regulated by the wsm, including pulse repetition, internal verification and margining of data. addresses and data are internally latched during write cycles. writing the appropriate command outputs array data, accesses the identifier codes or outputs status register data. interface software that initiates and polls progress of block erase, full chip erase, word/byte write and lock-bit configuration can be stored in any block. this code is copied to and executed from system ram during flash memory updates. after successful completion, reads are again possible via the read array command. block erase suspend allows system software to suspend a block erase to read/write data from/to blocks other than that which is suspend. word/byte write suspend allows system software to suspend a word/byte write to read data from any other flash memory array location. [awaol bottom boot [arg-a-11 fffff fboco f7fff ec%% ebcoo e-ifff a%? d8000 d7fff ceez cbmx) c7fff t%e b8coo b7fff bocoo affff abooo a7fff %% 98cm 97ef :z%$ 88ooo ufff 8woo 7ffff 78om 77fff ~~ 68wo 67fff 5% simm 57fff 5mo 4ffff 48ooo 47fff 40000 3ffff 38000 37fff 3m 2wff 28axl 27ff-f :ijez 18ooo 17ft-f dfe% 08mx) 07fff 07cal omm 06mo osfff 05cm mfff cmom) ojfff 03m 02fff 02ouo oifff 01000 oofff 00000 i 32kwhkb main block 30 i i 32kwhkb main block 29 i i 32kwhkb main block 28 1 i 32kw/64kb main block 22 i 32kwhkb main block 21 32kw164kb main block 20 32kwi64kb main block 19 32kwi64kb main block 18 32kw164kb main block 17 32kwl64kb main block 16 32kw164kb main block 15 32kw164kb main block 14 32kwhkb main block 7 32kw/64kb main block 6 32kw/64kb main block 5 32kwhkb main block 4 32kwhkb main block 3 32kwhkb main block 2 i 32kw/64kb main block 1 i 32kwi64kb main block 0 4kw/8kb parameter block 5 4kw/8kb parameter block 4 4kw/8kb parameter block 3 4kw/8kj3 parameter block 2 4kw/8kb parameter block 1 jkw18kb parameter block 0 4kw18kb boot block 1 4kwi8kb boot block? 0 1ftm-t lfooo0 ieftff iemxy) idffff idocm lcffff icoow ibftw iboocq iaffff 1&%? 19ooal iefff 18oow 17ffff 17moo i6ffff 16oom) 15ffff i5cqcm 14ffff 14ocfj.l i3ffff 13m 12ffff 12m iiffff 110000 ioffff iooooo offfff ofoooo oeffff oeomn odfttf ie% zie% obogoo oaffff oamxx) 09ffff o?janm obffff 08oxq 07ffff 07cwo 06ffff o6woo 05ffff 050000 04fltf 04owo 03ffff 03mx)o 02ffm 02m oiffff 010ool ox=fff ooecqo oodfff oocam oobfff ooacqo cqpfff 008ckm 007fff m co5fff elfi omoca wifff 000000 figure 3. memory map rev. 1.2
shari= lhfl6507 2.1 data protection when vc~iv,,~~, memory contents cannot be altered. the gui, with two-step block erase, full chip erase, word/byte write or lock-bit configuration command sequences, provides protection from unwanted operations even when high voltage is applied to v,,,. all write functions are disabled when v,, is below the write lockout voltage v,,, or when rp# is at v,. the device?s block locking capability provides additional protection from inadvertent code or data alteration by gating block erase, full chip erase and word/byte write operations. refer to table 5 for write protection alternatives. 3 bus operation the local cpu reads and writes flash memory in-system. all bus cycles to or from the flash memory conform to standard microprocessor bus cycles. 3.1 read information can be read from any block, identifier codes or status register independent of the vccw voltage. ri% can be at v, the first task is to write the appropriate read mode command (read array, read identifier codes or read status register) to the cui. upon initial device power-up or after exit from reset mode, the device automatically resets to read array mode. six control pins dictate the data flow in and out of the component: ce#, oe#, byte#, we#, rp# and wp#. ce# and oe# must be driven active to obtain data at the outputs. ce# is the device selection control, and when active enables the selected memory device. oe# is the data output (dq,,-dq,s) control and when active drives the selected memory data onto the i/o bus. byte# is the device i/o interface mde control. we# must be at v,,, rp# must be at vi,, and byte# and wp# must be at v, or vi,. figure 14, 15 illustrates read cycle. 3.2 output disable with oe# at a logic-high level (v,,), the device outputs are disabled. output pins (dqo-dq,,) are placed in a high-impedance state. 3.3 standby ce# at a logic-high level (vi,) places the device ii standby mode which substantially reduces device powe consumption. dqo-dqis outputs are placed in a high impedance state independent of oe#. if deselected during block erase, full chip erase, word/byte write or lock-bi configuration, the device continues functioning, ant consuming active power until the operation completes. 3.4 reset rp# at vi, initiates the reset mode. in read modes, rp#-low deselects the memory, place: output drivers in a high-impedance state and turns off al internal circuits. rp# must be held low for a minimum o 100 ns. time tphqv is required after return from rese mode until initial memory access outputs are valid. after this wake-up interval normal operation is restored. the cui is reset to read array mode and status register is set tc 80h. during block erase, full chip erase, word/byte write 01 lock-bit configuration modes, rp#-low will abort the operation. ry/by# remains low until the reset operatior is complete. memory contents being altered are no longei valid; the data may be partially erased or written. time tphwl is required after rp# goes to logic-high (vi,; before another command can be written. as with any automated device, it is important to asseri rp# during system reset. when the system comes out 01 reset, it expects to read from the flash memory. automated flash memories provide status information when accessed during block erase, full chip erase, word/byte write oi lock-bit configuration modes. if a cpu reset occurs with no flash memory reset, proper cpu initialization may not occur because the flash memory may be providing status information instead of array data. sharp?s flash memories allow proper cpu initialization following a system reset through the use of the rp# input. in this application, rp# is controlled by the same reset# signal that resets the system cpu. rev. 1.2
shari= lhfl6507 9 3.5 read identifier codes the read identifier codes operation outputs the manufacturer code, device code, block lock configuration codes for each block and the permanent lock configuration code (see figure 4). using the manufacturer and device codes, the system cpu can automatically match the device with its proper algorithms. the block lock and permanent lock configuration codes identify locked and unlocked blocks and permanent lock-bit setting. 3.6 write writing commands to the cui enable reading of device data and identifier codes. they also control inspection and clearing of the status register. when v,,=2.7v-3.6v and v ccw=vccwhl12~ the cui additionally controls block erase, full chip erase, word/byte write and lock-bit configuration. the block erase command requires appropriate command data and an address within the block to be erased. the full chip erase command requires appropriate command data and an address within the device. the word/byte write command requires the command and address of the location to be written. set permanent and block lock-bit commands require the command and address within the device (permanent lock) or block within the device (block lock) to be locked. the clear block lock-bits command requires the command and address within the device. the cui does not occupy an addressable memory location. it is written when we# and ce# are active. the address and data needed to execute a command are latched on the rising edge of we# or ce# (whichever goes high first). standard microprocessor write timings are used. figures 16 and 17 illustrate we# and ce# controlled write operations. 4 command definitions when the vccw voltage iv,,,,, read operations from the status register, identifier codes, or blocks are enabled. placing vccwh,,2 on vccw enables successful block erase, full chip erase, word/byte write and lock-bit configuration operations. device operations are selected by writing specific commands into the cui. table 3 defines these commands. bottom boot &-&i? ?l reserved ?ear f&&implementation reserved? for future iinpiementation (main blocks 1 through 29) offff ?. reserved: for future impiementation 08003 : --~----------------------------------- 08002 main block 0 lock configuration code -------**--t-------i------------------ 08001 :. rese&d for f&ure implementation main block 0 reserved: for future implementation 07002 1 parameter block 5 lock configuration code 1 ----*---,,,---*,--,,----1-------------- reserved f& future hplefnentation : &rameter biock 5 i (parameter blocks 1 through 4) reserv&?forfuture implementation parameter block 0 lock confieuration code 01003 olca? 01001 oloca oofff oooq4 ooai3 00002 00001 00000 reserved for future implementation boot block 1 lock configuration code ________-_-____*__--_*_____ yl for future zmp+nentation boot fjtixk i : d: for future hnphm&tion ?--j-------------ii_------------------ permanent lock configuration code ?: address a-1 don?t care. figure 4. device identifier code memory map rev. 1.2
sharp lhfl6jo7 jotes: . refer to dc characteristics. when vccw5v,,,,, memory contents can be read, but not altered. ,. x can be v, or vi, for control pins and addresses, and v,-,,, or vccwhir for v,,. see dc characteristics for vccwlk voltages. . ry/by# is v, when the wsm is executing internal block erase, full chip erase, word/byte write or lock-bit configuration algorithms. it is high z during when the wsm is not busy, in block erase suspend mode (with word/byte write inactive), word/byte write suspend mode or reset mode. ?. rf?# at gndk0.2v ensures the lowest power consumption. . see section 4.2 for read identifier code data. . command writes involving block erase, full chip erase, word/byte write or lock-bit configuration are reliably executed when vccw=vccwhiiz and v,,=2.lv-3.6v. . refer to table 3 for valid d,, during a write operation. . never hold oe# low and we# low at the same timing. rev. 1.2
shari= lhfl6507 11 table 3. command definition#o) set block lock-bit 2 8 write x 60h write ba oih clear block lock-bits 2 78 write x 60h write x doh set permanent lock-bit 2 9 write x 60h write x flh notes: 1. bus operations are defined in table 2.1 and table 2.2. 2. x=any valid address within the device. ia=identifier code address: see figure 4. ba=address within the block being erased. wa=address of memory location to be written. 3. srd=data read from status register. see table 6 for a description of the status register bits. wd=data to be written at location wa. data is latched on the rising edge of we# or ce# (whichever goes high first). id=data read from identifier codes. 4. following the read identifier codes command, read operations access manufacturer, device, block lock configuration and permanent lock configuration codes. see section 4.2 for read identifier code data. 5. if wp# is v,, boot blocks are locked without block lock-bits state. if wp# is v,,, boot blocks are locked by block lock- bits. the parameter and main blocks are locked by block lock-bits without wp# state. 6. either 40h or 10h are recognized by the wsm as the word/byte write setup. 7. the clear block lock-bits operation simultaneously clears all block lock-bits. 8. if the permanent lock-bit is set, set block lock-bit and clear block lock-bits commands can not be done. 9. once the permanent lock-bit is set, permanent lock-bit reset is unable. 10. commands other than those shown above are reserved by sharp for future device implementations and should not be used. rev. 1.2
sharp lhfl6507 12 i 4.1 read array command 4.3 read status register command upon initial device power-up and after exit from reset mode, the device defaults to read array mode. this operation is also initiated by writing the read array command. the device remains enabled for reads until another command is written, once the internal wsm has started a block erase, full chip erase, word/byte write or lock-bit configuration the device will not recognize the read array command until the wsm completes its operation unless the wsm is suspended via an erase suspend or word/byte write suspend command. the read array command functions independently of the v,,-w voltage and rp# can be v,,. 4.2 read identifier codes command the identifier code operation is initiated by writing the read identifier codes command. following the command write, read cycles from addresses shown in figure 4 retrieve the manufacturer, device, block lock configuration and permanent lock configuration codes (see table 4 for identifier code values). to terminate the operation, write another valid command. like the read array command, the read identifier codes command functions independently of the vccw voltage and rp# can be v,,. following the read identifier codes command, the following information can be read: table 4. identifier codes code manufacture code device code block lock configuration *block is unlocked *block is locked *reserved for future use address(*) data(31 [a,9-aol pq7-dqol oooooh boh oooolh e9h ba(?)+2 ~ :.:.:.:.:.:.:.:.:.:.:.:.:.:.:.:.:.:.:.:.:.:.:.:.:.:.:.. dq,=o dq,=l do, -, the status register may be read to determine when a bloc) erase, full chip erase, word/byte write or lock-bi configuration is complete and whether the operatior completed successfully. it may be read at any time b) writing the read status register command. after writing this command, all subsequent read operations output dan from the status register until another valid command is written. the status register contents are latched on the falling edge of oe# or ce#, whichever occurs. oe# or ce# must toggle to v,, before further reads to update the status register latch. the read status register command functions independently of the v,-w voltage. rp# can be vu-i. 4.4 clear status register command status register bits sr.5, sr.4, sr.3 or sr.1 are set to ?1?s by the wsm and can only be reset by the clear status register command. these bits indicate various failure conditions (see table 6). by allowing system software to reset these bits, several operations (such as cumulatively erasing multiple blocks or writing several words/bytes in sequence) may be performed. the status register may be polled to determine if an error occurred during the sequence. to clear the status register, the clear status register command (50h) is written. it functions independently of the applied vccw voltage. rp# can be v,,. this command is not functional during block erase or word/byte write suspend modes. j *device is unlocked *device is locked *reserved for future use dq,=o dq,=l dq1-7 note: 1. ba selects the specific block lock configuration code to be read. see figure 4 for the device identifier code memory map. 3. a-1 don?t care in byte mode. 2. dq,,-dq, outputs ooh in word mode. rev. 1.2
sharp lhf16507 13 4.5 block erase command erase is executed one block at a time and initiated by a two-cycle command. a block erase setup is first written, followed by an block erase confirm. this command sequence requires appropriate sequencing and an address within the block to be erased (erase changes all block data to ffffh/ffh). block preconditioning, erase, and verify are handled internally by the wsm (invisible to the system). after the two-cycle block erase sequence is written, the device automatically outputs status register data when read (see figure 5). the cpu can detect block erase completion by analyzing the output data of the ry/by# pin or status register bit sr.7. when the block erase is complete, status register bit sr.5 should be checked. if a block erase error is detected, the status register should be cleared before system software attempts corrective actions. the cui remains in read status register mode until a new command is issued. this two-step command sequence of set-up followed by execution ensures that block contents are not accidentally erased. an invalid block erase command sequence will result in both status register bits sr.4 and sr.5 being set to ?1?. also, reliable block erasure can only occur when v,,=2.7v-3.6v and vccw=vccwhir. in the absence of this high voltage, block contents are protected against erasure. if block erase is attempted while vccwlvccwlk, sr.3 and sr.5 will be set to ?1?. successful block erase requires for boot blocks that wp# is v,, and the corresponding block lock-bit be cleared. in parameter and main blocks case, it must be cleard the corresponding block lock-bit. if block erase is attempted when the excepting above conditions, sr.l and sr.5 will be set to ?1?. 4.6 full chip erase command this command followed by a confirm command erases all of the unlocked blocks. a full chip erase setup (30h) is first written, followed by a full chip erase confirm (doh). after a confirm command is written, device erases the all unlocked blocks block by block. this command sequence requires appropriate sequencing. block preconditioning, erase and verify are handled internally by the wsm invisible to the system). after the two-cycle full chip erase sequence is written, the device automatically outputs status register data when read (see figure 6). the cpu can letect full chip erase completion by analyzing the output lata of the ry/by# pin or status register bit sr.7. #hen the full chip erase is complete, status register bit jr.5 should be checked. if erase error is detected, the status register should be cleared before system software ittempts corrective actions. the cui remains in read status register mode until a new command is issued. it error is detected on a block during full chip erase operation, wsm stops erasing. full chip erase operation start from lower address block, finish the higher address block. full chip erase can not be suspended. this two-step command sequence of set-up followed by execution ensures that block contents are not accidentally erased. an invalid full chip erase command sequence will result in both status register bits sr.4 and sr.5 being set to ?1?. also, reliable full chip erasure can only occur when v,,=2.7v-3.6v and vccw=vccwhln. in the absence of this high voltage, block contents are protected against erasure. if full chip erase is attempted while vccw?vccwlk~ sr.3 and sr.5 will be set to ?1?. successful full chip erase requires for boot blocks that wp# is v,, and the corresponding block lock-bit be cleared. in parameter and main blocks case, it must be cleat-d the corresponding block lock-bit. if all blocks are locked, sr.1 and sr.5 will be set to ?1?. 4.7 word/byte write command word/byte write is executed by a two-cycle command sequence. word/byte write setup (standard 40h or alternate 10h) is written, followed by a second write that specifies the address and data (latched on the rising edge of we#). the wsm then takes over, controlling the word/byte write and write verify algorithms internally. after the word/byte write sequence is written, the device automatically outputs status register data when read (see figure 7). the cpu can detect the completion of the word/byte write event by analyzing the ry/by# pin or status register bit sr.7. when word/byte write is complete, status register bit sr.4 should be checked. if word/byte write error is detected, the status register should be cleared. the internal wsm verify only detects errors for ?1?s that do not successfully write to ?0?s. the cui remains in read status register mode until it receives another command. reliable word/byte writes can only occur when vcc=2.7v-3.6v and vccw=vccwhln. in the absence of this high voltage, memory contents are protected against word/byte writes. if word/byte write is attempted while vccwsvccwlk? status register bits sr.3 and sr.4 will be set to ?1?. successful word/byte write requires for boot blocks that wp# is v,, and the corresponding block lock- bit be cleared. in parameter and main blocks case, it must be cleard the corresponding block lock-bit. if word/byte write is attempted when the excepting above conditions, sr. 1 and sr.4 will be set to ?1?. rev. 1.2
sharp lhfl6507 14 4.8 block erase suspend command the block erase suspend command allows block-erase interruption to read or word/byte write data in another block of memory. once the block erase process starts, writing the block erase suspend command requests that the wsm suspend the block erase sequence at a predetermined point in the algorithm. the device outputs status register data when read after the block erase suspend command is written. polling status register bits sr.7 and sr.6 can determine when the block erase operation has been suspended (both will be set to ?1?). ry/by# will also transition to high z. specification twhrz2 defines the block erase suspend latency. when block erase suspend command write to the cui, if block erase was finished, the device places read array mode. therefore, after block erase suspend command write to the cui, read status register command (70h) has to write to cui, then status register bit sr.6 should be checked for places the device in suspend mode. at this point, a read array command can be written to read data from blocks other than that which is suspended. a word/byte write command sequence can also be issued during erase suspend to program data in other blocks. using the word/byte write suspend command (see section 4.9), a word/byte write operation can also be suspended. during a word/byte write operation with block erase suspended, status register bit sr.7 will return to ?0? and the ry/by# output will transition to vol. however, sr.6 will remain ?1? to indicate block erase suspend status. the only other valid commands while block erase is suspended are read status register and block erase resume. after a block erase resume command is written to the flash memory, the wsm will continue the block erase process. status register bits sr.6 and sr.7 will automatically clear and ry/by# will return to vol. after the erase resume command is written, the device automatically outputs status register data when read (see figure 8). v,,w must remain at v,,,,, (the same vccw level used for block erase) while block erase is suspended. rp# must also remain at v,,. wp# must also remain at vi, or v,, (the same wp# level used for block erase). block erase cannot resume until word/byte write operations initiated during block erase suspend have completed. if the period of from block erase resume command write to the cui till block erase suspend command write to the cui be short and done again and again, erase time be prolonged. 4.9 word/byte write suspend command the word/byte write suspend command allows word/byte write interruption to read data in other flash memory locations. once the word/byte write process starts, writing the word/byte write suspend command requests that the wsm suspend the word/byte write sequence at a predetermined point in the algorithm. the device continues to output status register data when read after the word/byte write suspend command is written. polling status register bits sr.7 and sr.2 can determine when the word/byte write operation has been suspended (both will be set to ?1?). ry/by# will also transition to high z. specification twhrzl defines the word/byte write suspend latency. when word/byte write suspend command write to the cui, if word/byte write was finished, the device places read array mode. therefore, after word/byte write suspend command write to the cui, read status register command (70h) has to write to cui, then status register bit sr.2 should be checked for places the device in suspend mode. at this point, a read array command can be written to read data from locations other than that which is suspended. the only other valid commands while word/byte write is suspended are read status register and word/byte write resume. after word/byte write resume command is written to the flash memory, the wsm will continue the word/byte write process. status register bits sr.2 and sr.7 will automatically clear and ry/by# will return to vol. after the word/byte write resume command is written, the device automatically outputs status register data when read (see figure 9). v,,, must remain at vccwhir (the same v,,, level used for word/byte write) while in word/byte write suspend mode. rp# must also remain at vi,. wp# must also remain at vi, or v,, (the same wp# level used for word/byte write). if me period of from word/byte write resume command write to the cui till word/byte write suspend command write to the cui be short and done again and again, write time be prolonged. rev. 1.2
sharp lhfl6507 15 4.10 set block and permanent lock-bit commands a flexible block locking and unlocking scheme is enabled via a combination of block lock-bits, a permanent lock-bit and wp# pin. the block lock-bits and wp# pin gates program and erase operations while the permanent lock-bit gates block-lock bit modification. with the permanent lock-bit not set, individual block lock-bits can be set using the set block lock-bit command. the set permanent lock-bit command, sets the permanent lock-bit. after the permanent lock-bit is set, block lock-bits and locked block contents cannot altered. see table 5 for a summary of hardware and software write protection options. set block lock-bit and permanent lock-bit are executed by a two-cycle command sequence. the set block or permanent lock-bit setup along with appropriate block or device address is written followed by either the set block lock-bit confirm (and an address within the block to be locked) or the set permanent lock-bit confirm (and any device address). the wsm then controls the set lock-bit algorithm. after the sequence is written, the device automatically outputs status register data when read (see figure io). the cpu can detect the completion of the set lock-bit event by analyzing the ry/by# pin output or status register bit sr.7. when the set lock-bit operation is complete, status register bit sr.4 should be checked. if an error is detected, the status register should be cleared. the cui will remain in read status register mode until a new command is issued. this two-step sequence of set-up followed by execution ensures that lock-bits are not accidentally set. an invalid set block or permanent lock-bit command will result in status register bits sr.4 and sr.5 being set to ?1?. also, reliable operations occur only when v,,=2.7v-3.6v and v ccw=vccwhl l2. in the absence of this high voltage, lock-bit contents are protected against alteration. a successful set block lock-bit operation requires that the permanent lock-bit be cleared. if it is attempted with the permanent lock-bit set, sr.l and sr.4 will be set to ?1? and the operation will fail. 4.11 clear block lock-bits command all set block lock-bits are cleared in parallel via the cleai block lock-bits command. with the permanent lock-bit not set, block lock-bits can be cleared using only the clear block lock-bits command. if the permanent lock-bit is set, block lock-bits cannot cleared. see table 5 for a summary of hardware and software write protection options. clear block lock-bits operation is executed by a two-cycle command sequence. a clear block lock-bits setup is first written. after the command is written, the device automatically outputs status register data when read (see figure 11). the cpu can detect completion of the clear block lock-bits event by analyzing the ry/by# pin output or status register bit sr.7. when the operation is complete, status register bit sr.5 should be checked. if a clear block lock-bit error is detected, the status register should be cleared. the cui will remain in read status register mode until another command is issued. this two-step sequence of set-up followed by execution ensures that block lock-bits are not accidentally cleared. an invalid clear block lock-bits command sequence will result in status register bits sr.4 and sr.5 being set to ?1?. also, a reliable clear block lock-bits operation can only occur when v,,=2.7v-3.6v and vccw=vccwhln. if a clear block lock-bits operation is attempted while vccw?vccwlk, sr.3 and sr.5 will be set to ?1?. in the absence of this high voltage, the block lock-bits content are protected against alteration. a successful clear block lock-bits operation requires that the permanent lock-bit is not set. if it is attempted with the permanent lock-bit set, sr.l and sr.5 will be set to ?1? and the operation will fail. if a clear block lock-bits operation is aborted due to v,,, or v,, transitioning out of valid range or rp# active transition, block lock-bit values are left in an undetermined state. a repeat of clear block lock-bits is required to initialize block lock-bit contents to known values. once the permanent lock-bit is set, it cannot be cleared. rev. 1.2
shari= lhf16jo7 16 4.12 block locking by the wp# an error, which will be reflected in the status register. for top configuration, the top two boot blocks are lockable. this boot block flash memory architecture features two hardware-lockable boot blocks so that the kernel code for the system can be kept secure while other blocks are programmed or erased as necessary. for the bottom configuration, the bottom tow boot blocks are lockable. if wp# is v,, and block lock-bit is not set, boot block can be programmed or erased normally (unless v,, is below v,,,,). wp# is valid only two boot blocks, other blocks are not affected. the lockable blocks are locked when wp#=v,; any program or erase operation to a locked block will result in operation block erase or word/byte write full chip erase set block lock-bit zlear block lock-bits set permanent lock-bit table 5. write protection alternatives all unlocked blocks are erased. x x x clear block lock-bits disabled. 0 x x clear block lock-bits enabled. 1 x x clear block lock-bits disabled. x x x set permanent lock-bit disabled. x x x set permanent lock-bit disabled. x x x set permanent lock-bit enabled. rev. 1.2
shari= lhfl6507 17 ?table 6. status register definition wsms 1 bess ( ecblbs 1 wbwslbs 1 vccws 1 wbwss 1 dps r 7 6 5 4 3 2 1 0 notes: sr.7 = write state machine status (wsms) check ry/by# or sr.7 to determine block erase, full chip 1 = ready erase, word/byte write or lock-bit configuration completion. 0 = busy sr.6-0 are invalid while sr.7=?0?. sr.6 = block erase suspend status (bess) 1 = block erase suspended 0 = block erase in progress/completed sr.5 = erase and clear block lock-bits status (ecblbs) 1 = error in block erase, full chip erase or clear block lock-bits if both sr.5 and sr.4 are ?1?s after a block erase, full chip erase or lock-bit configuration attempt, an improper command sequence was entered. 0 = successful block erase, full chip erase or clear block lock-bits sr.4 = word/byte write and set lock-bit status (wbwslbs) 1 = error in word/byte write or set block/permanent lock-bit 0 = successful word/byte write or set block/permanent lock-bit sr.3 does not provide a continuous indication of vccw level. the wsm interrogates and indicates the vccw level only after block erase, full chip erase, word/byte write or lock-bit configuration command sequences. sr.3 is not guaranteed to reports accurate feedback only when vccw+vccwhl/2. sr.3 = v,,, status (vccws) 1 = vccw low detect, operation abort 0 = v,,, ok sr.2 = word/byte write suspend status (wbwss) 1 = word/byte write suspended 0 = word/byte write in progress/completed sr. 1 = device protect status (dps) 1 = block lock-bit, permanent lock-bit and/or wp# lock detected, operation abort 0 = unlock sr. 1 does not provide a continuous indication of permanent and block lock-bit and wp# values. the wsm interrogates the permanent lock-bit, block lock-bit and wp# only after block erase, full chip erase, word/byte write or lock-bit configuration command sequences. it informs the system, depending on the attempted operation, if the block lock-bit is set, permanent lock-bit is set and/or wp# is v,,. reading the block lock and permanent lock configuration codes after writing the read identifier codes command indicates permanent and block lock-bit status. sr.0 = reserved for future enhancements (r) sr.0 is reserved for future use and should be masked out when polling the status register. rev. 1.: 1
shari= lhfl6507 18 write 70h write ?oh write doh. block address check if desired full status check procedure read status register data(see above) block erase error block erase successful slandby check sr.7 i=wsm ready o=wsm busy write erase setup data=?oh addr=x wri1e erase dau=wh confirm ad&within block to be erased read 1 repeat for subsequent block erasures. full status check can be done after each block em.se or after a sequsnce of block erasures. write ffh after the last aperation to place dence in read array mode. command comments check sr.3 i?vc~ error detrct check sr.1 l=device protect delen check sr.4.5 both i=command sequence fnot check sr.5 i=block erase error sr.5. sr.4, sr.3 and sr. i are only cleared by the clear status register command 10 cases where muluple blocks are erased before full sums is checked. if errcs is detected, clear the status register before attempting retry or ether error recovery. figure 5. automated block erase flowchart rev. 1.2
shari= lhf16507 fl?ll status check procedure read stalus reglater dat@ee above) command sequence read standby status regrster data check sr.7 l=wsm ready o=wsm busy write full chip erase setup dam=3oh ad&x write full chip erase coidiilil data=doh addr=x read standby status register data check sr.7 l=wsm ready o=wsm busy full status check can be done after each full chip erase. write ffh after the last operatmn to place dence m read anay mode. bus opaalion command comments 1? standby 1 check sr.3 i=vccw erra detect sr.5, sr.4 and sr.3 are only cleared by tbe clear status register command in cases where multiple blocks are erased before full status is checked. if error is detected, clear the status register before anemptmg retry or ahrr error recovery. figure 6. automated full chip erase flowchart rev. 1.2
sharp lip.1 6507 write 40h or ioh status register suspend word/byte full status check procedure read status regster data(see above) device protect &or word/byte write successful bus operation command colnlmi~ write read standby write setup wc&byte write dam=70h addrzx stau register data check sr.7 l=wsm ready qwsm busy data=4oh cs ioh addr=x w&e wdlbyte write dam=data to bc written addx=lccalioo to be written read status regrster data standby check sr.7 i=wsmready ozwsm busy repeat for subsequent wad/byte writes. sr full status check can be done after each wordmyte wile. or after a sequence of word/byte maes. write ffh after the last wordmy~e write operatron to place device m read array mode. bus oper.?tlo. command colnli.xus standby check sr.3 standby check sr.1 l=device protect dan suodby check sr.4 l=data wnte en.x sr.4, sr.3 and sr.1 are only cleared by the clear status register command in cases where multiple locatioos are written before full status is checked. if erm ui detected, clear the slatus register before attempting retry or &her error recovery. figure 7. automated word/byte write flowchart rev. 1.2
sharp lhfl6507 wrlre boh status register write doh write ffh k&j &i figure 8. block erase suspend/resume flowchart rev. 1.2
shari= swt write boh bus operario command i write wordlbp write data=boh suspend addr=x write read array data=frt addt=x write wordbyte write resume data=doh ad&x lhf16507 22 figure 9. word/byte write suspend/resume flowchart rev. 1.2
shari= lhfl6507 23 write 70h i read status writs 6oh writeoiwfih, block/device address check if desired full status check procedure device rotect error set lock-btt successful bus *ratioo command i wtt1e read standby read status registet dma=toh ad&x status regrster data check sr.7 l=wsm ready qwsm busy repeat for subsequent lock-bit set operatmns. full status check can be done after each lock-bit set operation or aftera sequence of lock-bit set operations. write ffh after the last lock-bit set opaation to place device m read array mcdz. bus operation command standby check sr.3 l=vccw error detect check sr.1 standby l=dsvice rotect detect permanent lock-btt is set (set block lack-bit operation) standby check sr.4.5 both i=command sequence error standby check sr.4 i=sst lock-bit error i i srs. sr.4. sr.3 and sr. 1 are only cleared by the cleat status register command in cases where multiple lock-bits iye set before full status is checked. ifsrra is detected, clear the status registsr hsfore attempting retry or other etmr recovery. figure 10. set block and permanent lock-bit flowchart rev. 1.2
sharp r lhfl6507 24 1 full status check procedure read status register at&see above) device raect error command sequence clear block lock-bits clear block lock-bits successful write read status rf!gister data7oh addr=x i i read status register data standby check sr.7 i=wsm ready oswsm busy w&e clear block dat.x+oh lock-bits setup addr=x write clear block lock-biu confirm daia=dqh ad&x i ! read status regwer data write ffh after the clear block lock-bits operation to place device in read anay mode. sr.5, sr.4. sr.3 and sri are only cleared by the clear status register command. if ena in detected. clea tie status register before attempting retry or other error recovery. figure 11. clear block lock-bits flowchart rev. 1.2
shari= lhfl6507 25 5 design considerations 5.1 three-line output control the device will often be used in large memory arrays. sharp provides three control inputs to accommodate multiple memory connections. three-line control provides for: a. lowest possible memory power dissipation. b. complete assurance that data bus contention will not occur. to use these control inputs efficiently, an address decoder should enable ce# while oe# should be connected to all memory devices and the system?s read# control line. this assures that only selected memory devices have active outputs while deselected memory devices are in standby mode. rp# should be connected to the system powergood signal to prevent unintended writes during system power transitions. powergood should also toggle during system reset. 5.2 ry/by# and wsm polling ry/by# is an open drain output that should be connected to v,, by a pull up resistor to provides a hardware method of detecting block erase, full chip erase, word/byte write and lock-bit configuration completion. it transitions low after block erase, full chip erase, word/byte write or lock- bit configuration commands and returns to v,, (while ry/by# is pull up) when the wsm has finished executing the internal algorithm. ry/by# can be connected to an interrupt input of the system cpu or controller. it is active at all times. ry/by# is also high z when the device is in block erase suspend (with word/byte write inactive), word/byte write suspend or reset modes. 5.3 power supply decoupling flash memory power switching characteristics require careful device decoupling. system designers are interested in three supply current issues; standby current levels. active current levels and transient peaks produced by falling and rising edges of ce# and oe#. transient current magnitudes depend on the device outputs? capacitive and inductive loading. two-line control and proper decoupling capacitor selection will suppress transient voltage peaks. each device should have a o.lpf ceramic capacitor connected between its v,, and gnd and between its vccw and gnd. these high-frequency, low inductance capacitors should be placed as close as possible to package leads. additionally, for every eight devices, a 4.7nf electrolytic capacitor should be placed at the array?s power supply connection between v,, and gnd. the bulk capacitor will overcome voltage slumps caused by pc board trace inductance. 5.4 vccw trace on printed circuit boards updating flash memories that reside in the target system requires that the printed circuit board designer pay attention to the vccw power supply trace. the vccw pin supplies the memory cell current for word/byte writing and block erasing. use similar trace widths and layout considerations given to the v,, power bus. adequate vccw supply traces and decoupling will decrease vccw voltage spikes and overshoots. 5.5 vcc, vccw, rp# transitions block erase, full chip erase, word/byte write and lock-bit configuration are not guaranteed if vccw falls outside of a valid vccwh1,2 range, v,, falls outside of a valid 2.7v- 3.6v range, or rp##v,,. if v,,w error is detected, status register bit sr.3 is set to ?1? along with sr.4 or sr.5, depending on the attempted operation. if rp# transitions to v, during block erase, full chip erase, word/byte write or lock-bit configuration, ry/by# will remain low until the reset operation is complete. then, the operation will abort and the device will enter reset mode. the aborted operation may leave data partially altered. therefore, the command sequence must be repeated after normal operation is restored. device power-off or rp# transitions to v, clear the status register. the cui latches commands issued by system software and is not altered by vccw or ce# transitions or wsm actions. its state is read array mode upon power-up, after exit from reset mode or after v,, transitions below v,,,. rev. 1.2
sharp lhfl6507 26 5.6 power-up/down protection the device is designed to offer protection against accidental block erase, full chip erase, word/byte write or lock-bit configuration during power transitions. upon power-up, the device is indifferent as to which power supply (vccw or v,,) powers-up first. internal circuitry resets the cui to read array mode at power-up. a system designer must guard against spurious writes for v,, voltages above vlko when vccw is active. since both we# and ce# must be low for a command write, driving either to v,, will inhibit writes. the gui?s two- step command sequence architecture provides added level of protection against data alteration. in-system block lock and unlock capability prevents inadvertent data alteration. the device is disabled while rp#=v, regardless of its control inputs state. 5.7 power dissipation when designing portable systems, designers must consider battery power consumption not only during device operation, but also for data retention during system idle time. flash memory?s nonvolatility increases usable battery life because data is retained when system power is removed. 5.8 data protection method noises having a level exceeding the limit specified in the specification may be generated under specific operating conditions on some systems. such noises, when induced onto we# signal or power supply, may be interpreted as false commands, causing undesired memory updating. ta protect the data stored in the flash memory against unwanted overwriting, systems operating with the flash memory should have the following write protect designs, as appropriate: 1) protecting data in specific block when a lock bit is set, the corresponding block (includes the 2 boot blocks) is protected against overwriting. by setting a wp# to low, only ?the 2 boot blocks can be protected against overwriting. by using this feature, the flash memory space can be divided into the program section (locked section) and data section (unlocked section). the permanent lock bit can be used to prevent false block bit setting. for further information on setting/resetting lock-bit, refer to the specification. (see chapter 4.10 and 4.11.) 2) data protection through vccw when the level of vccw is lower than vccwlk (lockout voltage), write operation on the flash memory is disabled. all blocks are locked and the data in the blocks are completely write protected. for the lockout voltage, refer to the specification. (see chapter 62.3.) 3) data protection through rp# when the rp# is kept low during read mode, the flash memory will be deep-power-down mode, then write protecting all blocks. when the rp# is kept low during power up and power down sequence such as voltage transition, write operation on the flash memory is disabled, write protecting all blocks. for the details of rp# control, refer to the specification. (see chapter 5.6 and 6.2.7.) rev. 1.2
sharp lhfl6507 27 6 electrical specifications 6.1 absolute maximum ratings* operating temperature during read, block erase, full chip erase, word/byte write and lock-bit configuration . . . . . . . . . . . . . -40c to +85?c(?) storage temperature during under bias . . . . . . . . . . . .._................. -40c to +85?c during non bias . . . .._.......................... -65c to +125?c voltage on any pin (except v,, and v,,,) ._......... -0.5v to v,,+o.5v(*) v,, supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.2v to +4.6v(*) vccw supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . -0.2v to +i 3.0v(*v3) output short circuit current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10on1a(~) *warning: stressing the device beyond the ?absolute maximum ratings? may cause permanent damage. these are stress ratings only. operation beyond the ?operating conditions? is not recommended and extended exposure beyond the ?operating conditions? may affect device reliability. notes: 1. operating temperature is for extended temperature product defined by this specification. 2. all specified voltages are with respect to gnd. minimum dc voltage is -0.5v on input/output pins and -0.2v on v,, and vccw pins. during transitions, this level may undershoot to -2.ov for periods c20ns. maximum dc voltage on input/output pins are vcc+0.5v which, during transitions, may overshoot to vcc+2.0v for periods c20ns. 3. maximum dc voltage on vccw may overshoot to +13.ov for periods c20ns. applying 12vko.6v to v,,w during erase/write can only be done for a maximum of 1000 cycles on each block. vccw may be connected to 12v&.6v for a total of 80 hours maximum. 4. output shorted for no more than one second. no more than one output shorted at a time. 6.2 operating conditions temperature and v,, operating conditions symbol parameter min. max. unit test condition ta operating temperature -40 +85 ?c ambient temperature v,, vcc supply voltage (2.7v-3.6v) 2.7 3.6 v 5.2.1 capacitance(l) symbol parameter c,, input capacitance co? votz: output capacitance 1. sampled, not 100% tested. t,=+25?c, f=imhz vp. max. 7 10 9 12 unit condition pf v,=o.ov pf v,,,=o.ov rev. 1.2
shari= lhf16507 28 .2.2 ac input/output test conditions ~tqz=$z=+t ac test inputs are driven at 2.7v for a logic ?1? and o.ov for a logic ?0?. input timing begins, and output timing ends, at 1.35v. input rise and fat1 times (10% to 90%) 40 ns. figure 12. transient input/output reference waveform for v,,=2.7v-3.6v test configuration capacitance loading value test configuration c,(pf) v,,=2.7v-3.6v 50 device under 0 out test cl includes jig - capacitance cl s - figure 13. transient equivalent testing load circuit rev. 1.2
shari= lhf16507 29 5.2.3 dc characteristics dc characteristics test conditions vcc=vccmax. v,=vcc or gnd v,,=v,,max. vout=vcc or gnd cmos level inputs v,,=v,,max. ce#=rp#=vc+0.2v ttl level inputs v,c=vccmax. ce#=rp#=v,, cmos level inputs v,,=v,,max. ce#=gnd&.2v rp#=gndk0.2v iou,(ry/by#)=oma cmos level inputs vcc=vccmax., ce#=gnd f=smhz, iout=oma ttl level inputs v,,=v,,max., ce#=gnd f=smhz, i,,,=oma vccw=2.7v-3.6v vccw=l 1.4v- 12.6v vccw=2.7v-3.6v v,,,=l1,4v-12.6v parameter sym. il1 unit cla cla input load current 1 --j-e il0 kcs output leakage current 1 v,, standby current 1,3,6 ?ccas v,, auto power-save current 1,5,6 ?ccd v,, reset power-down current 1 2 15 0.2 2 2 15 2 15 ma ?cc, vcc read current ma n-l4 1 v,, block erase, full chip erase or kcw ma ma kce n-l4 ma ma kcws [cces [ccws bvr &was &vd &ww ce#=v, +2 +15 10 200 t 0.1 5 0.1 5 12 40 vccw~vcc vccw?vcc cmos level inputs vcc=vccmax. ce#=gnd&.%v rp#=gndk0.2v v ccw=2.7v-3.6v v ccw=l 1.4v-12.6v v ccw=2.1v-3.6v v ccw=11.4v-12.6v vccw auto power-save current 1,5,6 jccw reset power-down current 1 iccw word/byte write or set lock- 1,7 3it current jccw block erase, full chip erase 177 )r clear block lock-bits current jccw word/byte write or 1 3lock erase suspend current ma ?-j-g) ma ma ma cla &we ccwws ccwes i 10 200 v ccw=vccwhir rev. 1.2
sharp lhfl6507 dc characteristics (continued) \totes: 1. all currents are in rms unless otherwise noted. typical values at nominal v,, voltage and ta=+25?c. 2. kcws and ?cces are specified with the device de-selected. if read or word/byte written while in erase suspend mode, the device?s current draw is the sum of i,,,, or i,,,, and i,,, or i,,, respectively. 3. includes ry/by#. 4. block erases, full chip erase, word/byte writes and lock-bit configurations are inhibited when vccwivccwlk, and not f;rr;yd in the range between vccwlk(max.) and vccwr..rl(min.), between vccwht(max.) and vccww(min.) and ccw&n=.). 5. the automatic power savings (aps) feature is placed automatically power save mode that addresses not switching more than 300ns while read mode. 6. about all of pin except describe test conditions, cmos level inputs are either vccd.2v or gnd&.2v, ttl level inputs are either v,, or v,,. 7. sampled, not 100% tested. 8. applying 12v&.6v to vccw during erase/write can only be done for a maximum of 1000 cycles on each block. vccw may be connected to 12v&.6v for a total of 80 hours maximum. rev. 1.2
sharp lhfl6507 6.2.4 ac characteristics - read-only operations(i) v,,=2,7v-3.6v, t,=-40?c to +85?c sym. parameter notes 1 min. unit read cycle time i ) max. 1 atiaii t rl.rx. i 70 ns tavov address to output delay 70 ns notes: 1. see ac input/output reference waveform for maximum allowable input slew rate. 2. oe# may be delayed up to telqv-klqv 3. sampled, not 100% tested. after the falling edge of ce# without impact on telqv. 4. if byte# transfer during reading cycle, exist the regulations separately. rev. 1.2
sharp lhfl6507 32 device standby address selection data valid figure 14. ac waveform for read operations rev. 1.2
shari= lhf16507 standby device address selection data valid bytewd figure 15. byte# timing waveform rev. 1.2
shari= lhfl6507 6.2.5 ac characteristics - write operations(l) i svm. i v,,=2.lv-3.6v, t,=-40c to +85?c parameter 1 notes 1 min. 1 max. 1 unit 1 tavav write cycle time tphwl rp# high recovery to we# going low telwl ce# setup to we# going low 70 ns 2 1 p 10 ns twlwh we# pulse width 40 ns ,hwh wp#vib setup to we# going high 2 100 ns tovvl vccw hold from valid srd, ry/by# high z 2,4 0 ns tovsl wp# v,, hold from valid srd, ry/by# high z 2,4 0 ns tfvwh byte# setup to we# going high 5 40 ns fwhfv byte# hold from we# high 5 70 ns notes: 1. read timing characteristics during block erase, full chip erase, word/byte write and lock-bit configuration operations are the same as during read-only operations. refer to ac characteristics for read-only operations. 2. sampled, not 100% tested. 3. refer to table 3 for valid a,, and d,, for block erase, full chip erase, word/byte write or lock-bit configuration. 4. vccw should be held at vccwhr,z until determination of block erase, full chip erase, word/byte write or lock-bit configuration success (sr.1/3/4/5=0). 5. if byte# switch during reading cycle, exist the regulations separately. rev. 1.2
sharp 1 2 3 4 5 6 e--o-- vih addresses(a) vu ceme) oe#(g) data(diq) byte?+(f) vih vu vih vu vih vih vu vih ry/by#(r) (sr.7) vih i i rp#(p) i i i lhfl6507 35 notes: 1. vcc power-up and standby. 2. write each setup command. 3. write each confirm command or valid address and data. 4. automated erase or program delay. 5. read stahn register data. 6. write read array command. figure 16. ac waveform for we#-controlled write operations rev. 1.2
shari= lhfl6507 62.6 alternative ce#-controlled writes(l) i tovsl wp# v,, hold from valid srd, ry/by# high z 24 0 ns tfveh byte# setup to ce# going high 5 40 ns ~ fehfv byte# hold from ce# high 5 70 ns notes: 1. in systems where ce# defines the write pulse width (within a longer we# timing waveform), all setup, hold, and inactive we# times should be measured relative to the ce# waveform. 2. sampled, not 100% tested. 3. refer to table 3 for valid a,, and d,, for block erase, full chip erase, word/byte write or lock-bit configuration. 4. vccw should be held at v,,,br,, until determination of block erase, full chip erase, word/byte write or lock-bit configuration success (sr. l/3/4/5=0). 5. if byte# switch during reading cycle, exist the regulations separately. rev. 1.2
shari= lhfl6jo7 addresses(a) data(d/q) notes: 1. vcc power-up and standby. 2. write each setup command. 3. write each confirm command or valid address and data. 4. automated erase or program delay. 5. read status register data. 6. write read array command. figure 17. ac waveform for ce#-controlled write operations rev. 1.2
shari= lhf16507 38 6.2.7 reset operations reset ac specifications sym. parameter notes min. max. unit tplph rp# pulse low time (if rp# is tied to vcc, this specification is not applicable) 100 ns tplrz rp# low to reset during block erase, full chip erase, word/byte write or lock-bit configuration 12 30 w tr noes: v,, 2.7v to rp# high 3 100 ns 1. if rp# is asserted while a block erase, full chip erase, word/byte write or lock-bit configuration operation is not executing, the reset will complete within 1oons. 2. td.;et time, tphqv, is required from the later of ry/by#(sr.7) going high z(?1?) or rp# going high until outputs are 3. when the device power-up, holding rp# low minimum 1oons is required after v,, has been in predefined range and also has been in stable there. high z ry/by#(r) (?1?) (sr.7) vol (?0?) vih rwp) vil (a)reset during read array mode high z ry/by#(r) (?1?) (sr.7) vol (?0?) vih rw? vil (b)reset during block erase, full chip erase, word/byte write oc lock-bit configuration 2.7v i vcc vil - tzvph - vih rwp) i vil 7- (c)rp# rising timing figure 18. ac waveform for reset operation rev. 1.2
shari= lhfl6507 39 i.2.8 block erase, full chip erase, word/byte write and lock-bit configuration performance(3) v,,=2.7v-3.6v, t,=-40c to +85?c parameter set lock-bit time iotes: typical values measured at ta=+25?c and v,,=3.ov, v,,,- -3.ov or 12.ov. assumes corresponding lock-bits are not set. subject to change based on device characterization. excludes system-level overhead. sampled but not 100% tested. rev. 1.2
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